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CH7007A
CHRONTEL
Digital PC to TV Encoder with MacrovisionTM
Features
* Supports Macrovision 7.X anti-copy protection * Support for low voltage interface to VGA controller * Universal digital interface accepts YCrCb (CCIR656) or RGB (15, 16 or 24-bit multiplexed) video data in both non-interlaced and interlaced formats * TrueScale TM rendering engine supports underscan operations for various graphic resolutions * Enhanced text sharpness and adaptive flicker removal with up to 5-lines of filtering * Enhanced dot crawl control and area reduction * Fully programmable through I 2 C port * Supports NTSC, NTSC-EIA (Japan), and PAL (B, D, G, H, I, M and N) TV formats * Provides Composite, S-Video and SCART outputs * Auto-detection of TV presence * Programmable power management * 9-bit video DAC outputs * Complete Windows and DOS driver software * Offered in 44-pin PLCC, 44-pin TQFP
TM
General Description
Chrontel's CH7007 digital PC to TV encoder is a standalone integrated circuit which provides a PC 99 compliant solution for TV output. Suggested application use with the Intel 810 chipset and Intel 810E chipset.* It provides a universal digital input port to accept a pixel data stream from a compatible VGA controller (or equivalent) and converts this directly into NTSC or PAL TV format. This circuit integrates a digital NTSC/PAL encoder with 9-bit DAC interface, and new adaptive flicker filter, and high accuracy low-jitter phase locked loop to create outstanding quality video. Through its TrueScaleTM scaling and deflickering engine, the CH7007 supports full vertical and horizontal underscan capability and operates in 5 different resolutions including 640x480 and 800x600. A new universal digital interface along with full programmability make the CH7007 ideal for system-level PC solutions. All features are software programmable 2 through a standard I C port, to enable a complete PC solution using a TV as the primary display.
Patent number 5,781,241 Patent number 5,914,753
LINE MEMORY
YUV-RGB CONVERTER
RGB-YUV CONVERTER DIGITAL D[11:0] PIXEL DATA INPUT INTERFACE TRUE SCALE SCALING & DEFLICKERING ENGINE NTSC/PAL ENCODER & FILTERS Y/R TRIPLE DAC C/G CVBS/B
SYSTEM CLOCK
ISET
GPIO[1:0]
I2 C REGISTER & CONTROL BLOCK
PLL
TIMING & SYNC GENERATOR
SC
SD
RESET*
XCLK*
H
V
XI/FIN
XO CSYNC P-OUT DS/BCO
Figure 1: Functional Block Diagram
201-0000-002 Rev. 2.7, 08/23/2000 *Intel 810 and Intel 810E are Trademarks of Intel Corp 1
CHRONTEL
CH7007A
DS/BCO 41
DVDD2
XCLK*
P-OUT
DGND
6
5
4
3
2
1
44
43
42
D[1] D[2] D[3] D[4] DVDD D[5] D[6] DGND] D[7] D[8] D[9]
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
40 39 38 37 36
AGND
XCLK
VREF
D0]
H
V
XO XI/FIN AVDD DVDD RESET* DGND SC SD VDD ISET GND
CHRONTEL CH7007
35 34 33 32 31 30 29
DVDD
CSYNC
DGND
GND
CVBS
C
D[10]
D[11]
GPIO[0]
Figure 2: 44-Pin PLCC
2
GPIO[1]
Y
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CH7007A
DS/BCO 35
DVDD2
P-OUT
XCLK*
DGND
44
43
42
41
40
39
38
37
36
D[1] D[2] D[3] D[4] DVDD D[5] D[6] DGND] D[7] D[8] D[9]
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
34 33 32 31 30
AGND
XCLK
VREF
D0]
H
V
XO XI/FIN AVDD DVDD RESET* DGND SC SD VDD ISET GND
CHRONTEL CH7007
29 28 27 26 25 24 23
CVBS
D[10]
D[11]
GPIO[0]
GPIO[1]
DVDD
CSYNC
DGND
GND
Figure 3: 44-Pin TQFP
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C
Y
3
CHRONTEL
Table 1. Pin Descriptions
44-Pin PLCC
1
CH7007A
Type
In/Out
44-Pin TQFP
39
Symbol
VREF Reference Voltage Input
Description
The VREF pin inputs a reference voltage of DVDD2/2. The signal is derived externally through a resistor divider and decoupling capacitor, and will be used as a reference level for data and sync inputs. 2 40 In XCLK External Clock Input This input along with XCLK* will form a differential clock input. For applications where a differential clock is not available, the XCLK* pin should be connected to the VREF pin. 3 4 41 42 In In/Out XCLK* H External Clock Input* See XCLK description Horizontal Sync Input/Output When the SYO bit is low, this pin accepts a horizontal sync input. The level is 0 to DVDD2, with VREF as the threshold level. When the SYO bit is high, the device will output a horizontal sync pulse. The output is driven from the DVDD supply. 5 43 In/Out V Vertical Sync Input/Output When the SYO bit is low, this pin accepts a vertical sync input. The level is 0 to DVDD2 with VREF as the threshold level. When the SYO bit is high, the device will output a vertical sync pulse. The output is driven from the DVDD supply. 6-10,1213,15-19 20-21 44,1-4,67,9-13 14-15 In D[0]-D[11] Data [0] through Data [11] Inputs These pins accept 12 data inputs from the graphics controller. The level is 0 to DVDD2, with VREF as the threshold level. In/Out GPIO[0] GPIO[1] 23 17 Out CSYNC General Purpose Input/Output [0-1] and Internal pull-up These pins provide general purpose I/O's controlled via the IIC bus, registers 1Bh and 1Ch, bits 7 and 6. The internal pull-up is to the DVDD supply. Composite Sync Output A 75 termination resistor with short traces should be attached between CSYNC and ground for optimum performance. In SCART mode, this pin outputs the composite sync signal. Composite Video Output/Blue Output A 75 termination resistor with short traces should be attached between CVBS and ground for optimum performance. In normal operating modes other than SCART, this pin outputs the composite video signal. In SCART mode, this pin outputs the blue signal.
26
20
Out
CVBS/B
27
21
Out
C/G
Chroma Output/Green Output
A 75 termination resistor with short traces should be attached between C and ground for optimum performance. In normal operating
modes other than SCART, this pin outputs the chroma video signal. In SCART mode, this pin outputs the green signal.
28 22 Out Y/R
Luma Output / Red Output
A 75 termination resistor with short traces should be attached between Y and ground for optimum performance. In normal operating
modes other than SCART, this pin outputs the luma video signal. In SCART mode, this pin outputs the red signal.
30 24 In ISET
Current Set Resistor Input This pin sets the DAC current. A 360 ohm resistor should be connected between this pin and GND using short and wide traces.
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Table 1. Pin Descriptions
44-Pin PLCC
32
CH7007A
Type
In/Out
44-Pin TQFP
26
Symbol
SD
Description Serial Data Input/Output This pin functions as the serial data pin of the I2 C interface port, and uses the DVDD supply. (see the I 2C Port Operation section for details) Serial Clock Input This pin functions as the serial clock pin of the I2 C interface port, and uses the DVDD supply. (see the I 2C Port Operation section for details) Reset* Input
When this pin is low, the CH7007 is held in the power-on reset condition. When this pin is high, the device operates normally and reset is controlled through the I 2C register.
33
27
In
SC
35
29
In
RESET*
38
32
In
XI/FIN
Crystal Input/External Reference Input A parallel resonance 14.31818MHz crystal should be attached between this pin and XO. However, an external CMOS clock can be attached to XI/FIN. Crystal Output A parallel resonance 14.31818MHz +20ppm crystal should be attached between this pin and XI/FIN. However, if an external CMOS clock is attached to XI/FIN, XO should not be connected. Data start (input)/Buffered Clock (output) In normal operating modes, when configured as an input, the rising edge of this signal identifies the first active pixel of data for each active line. The level is 0 to DVDD2, with VREF as the threshold level. When configured as an output this pin provides a buffered clock output, driven by the DVDD supply. The output clock can be selected using the BCO register (17th) (see Registers and Programing).
39
33
Out
XO
41
35
In/Out
DS/BCO
43
37
Out
P-OUT
Pixel Clock Output This pin provides a pixel clock signal to the VGA controller (adjustable as 1X, 2X and 3X) and is driven from the DVDD2 supply. This clock will only be provided in master clock modes, and will be tri-stated otherwise, (see the section on Digital Video Interface and Registers and Programming for more details). The capacitive loading on this pin should be kept to a minimum. Digital Supply Voltage Digital Ground DAC DAC Supply Voltage PLL Supply Voltage PLL Ground I/O SUPPLY VOLTAGE Digital supply voltage for the P-OUT
11,22,36 14,24,34, 42 25,29 31 37 40 44
5,16,30 8,18,28, 36 19,23 25 31 34 38
Power Power Power Power Power Power Power
DVDD DGND GND VDD AVDD AGND DVDD2
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Digital Video Interface
CH7007A
The CH7007 digital video interface provides a flexible digital interface between a computer graphics controller and the TV encoder IC forming the ideal quality/cost configuration for performing the TV-output function. This digital interface consists of up to 12 data signals and 4 control signals, all of which are subject to programmable control through the CH7007 register set. This interface can be configured as 8 or 12-bit inputs operating in multiplexed mode. It will also accept either YCrCb or RGB (15, 16 or 24-bit color depth) data formats and will accept both non-interlaced and interlaced data formats. A summary of the input data format modes is as follows: Table 2. Input Data Formats
Bus Width Transfer Mode Color Space and Depth Format Reference
8-bit 8-bit 8-bit 12-bit 12-bit
2X-multiplexed 2X-multiplexed 2X-multiplexed 2X-multiplexed 2X-multiplexed
RGB 15-bit RGB 16-bit YCrCb (24-bit) RGB 24 RGB 24
5-5-5 over two bytes 5-6-5 over two bytes Cb,Y0,Cr,Y1,(CCIR656 style) 8-8-8 over two words - `C' version 8-8-8 over two words - `I' version
The clock and timing signals used to latch and process the incoming pixel data is dependent upon the clock mode. The CH7007 can operate in either master (the CH7007 generates a pixel frequency which is either returned as a phase-aligned pixel clock or used directly to latch data), or slave mode (the graphics chip generates the pixel clock). The pixel clock frequency will change depending upon the active image size (e.g., 640x480 or 800x600), the desired output format (NTSC or PAL), and the amount of scaling desired. The pixel clock may be requested to be 1X, 2X or 3X the pixel data rate (subject to a 100MHz frequency limitation). In the case of a 1X pixel clock the CH7007 will automatically use both clock edges, if a multiplexed data format is selected. Sync Signals: Horizontal and vertical sync signals will normally be supplied by the VGA controller, but may be selected to be generated by the CH7007. In the case of CCIR656 style input (IDF = 9), embedded sync may also be used. In each case, the period of the horizontal sync should be equal to the duration of the pixel clock, times the first value of the (Total Pixels/line x Total Lines/Frame) column of Table13 on page 29 (Display Mode Register 00H description). The leading edge of the horizontal sync is used to determine the start of each line. The Vertical sync signal must be able to be set to the second value in the (Total Pixels/Line x Total Lines/Frame) column of Table13 on page 29. Master Clock Mode: The CH7007 generates a clock signal (output at the P-OUT pin) which will be used by the VGA controller as a frequency reference. The VGA controller will then generate a clock signal which will be input via the XCLK input. This incoming signal will be used to latch (and de-multiplex, if required) incoming data. The XCLK input clock rate must match the input data rate, and the P-OUT clock can be requested to be 1X, 2X or 3X the pixel data rate. As an alternative, the P-OUT clock signal can also be used as the input clock signal (connected directly to the XCLK input) to latch the incoming data. If this mode is used, the incoming data must meet setup and hold times with respect to the XCLK input (with the only internal adjustment being XCLK polarity). Slave Clock Mode: The VGA controller will generate a clock which will be input to the XCLK pin (no clock signal will be output on the P-OUT pin). This signal must match the input data rate, must occur at 1X, 2X or 3X the pixel data rate, and will be used to latch (and de-multiplex if required) incoming data. Also, the graphics IC transmits back to the TV encoder the horizontal and vertical timing signals, and pixel data, each of which must meet the specified setup and hold times with respect to the pixel clock. Pixel Data: Active pixel data will be expected after a programmable number pixels times the multiplex rate after the leading edge of Horizontal Sync. In other words, specifying the horizontal back porch value (as a pixel count), plus horizontal sync width, will determine when the chip will begin to sample pixels.
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Input Data Formats
CH7007A
The XCLK and XCLK* signals are used to latch data from the graphics chip. Data can be latched coincident with the rising edge of XCLK, falling edge of XCLK, or both edges, depending upon register settings of XCM and MCP. The input data format is shown in Figure4 The Pixel Data bus represents an 8 or 12-bit multiplexed data stream, . which contains either RGB or YCrCb formatted data. In IDF settings of 4, 5, 7, 8 and 9, the input data rate is 2X pixel clock, and each pair of Pn values (e.g., P0a and P0b) will contain a complete pixel, encoded as shown in the tables below. When the input is YCrCb, the color-difference data will be transmitted at half the data rate of the luminance data, with the sequence being set as Cb0, Y0, Cr0, Y1 where Cb0,Y0,Cr0 refers to co-sited luminance and color-difference samples -- and the following Y1 byte refers to the next luminance sample, per CCIR656 standards. However, the clock frequency is dependent upon the current mode, not 27MHz, as specified in CCIR656.
HS SAV
(DSEN=0)
DS / BCO XCLK (XCM=01) XCLK* (XCM=01) XCLK (XCM=00) XCLK* (XCM=00)
D[11:0]
P0a
P0b
P1a
P1b
P2a
P2b
When DSEN=1(bit 4 of register 1Ch), SAV should be set to 11d.
Figure 4: Non-multiplexed Data Transfers
Table 3. RGB 8-bit Multiplexed Mode
IDF# Format Pixel# Bus Data D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] P0a G0[2] G0[1] G0[0] B0[4] B0[3] B0[2] B0[1] B0[0] 7 RGB 5-6-5 P0b R0[4] R0[3] R0[2] R0[1] R0[0] G0[5] G0[4] G0[3] P1a G1[2] G1[1] G1[0] B1[4] B1[3] B1[2] B1[1] B1[0] P1b R1[4] R1[3] R1[2] R1[1] R1[0] G1[5] G1[4] G1[3] P0a G0[2] G0[1] G0[0] B0[4] B0[3] B0[2] B0[1] B0[0] 8 RGB 5-5-5 P0b x R0[4] R0[3] R0[2] R0[1] R0[0] G0[4] G0[3] P1a G1[2] G1[1] G1[0] B1[4] B1[3] B1[2] B1[1] B1[0] P1b x R1[4] R1[3] R1[2] R1[1] R1[0] G1[4] G1[3]
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CH7007A
Table 4. RGB 12-bit Multiplexed Mode
IDF# Format Pixel# Bus Data 4 12-bit RGB (12-12) P0b P1a R0[7] G1[3] R0[6] G1[2] R0[5] G1[1] R0[4] G1[0] R0[3] B1[7] R0[2] B1[6] R0[1] B1[5] R0[0] B1[4] G0[7] B1[3] G0[6] B1[2] G0[5] B1[1] G0[4] B1[0] 5 12-bit RGB (12-12) P0b P1a R0[7] G1[4] R0[6] G1[3] R0[5] G1[2] R0[4] B1[7] R0[3] B1[6] G0[7] B1[7] G0[6] B1[4] G0[5] B1[3] R0[2] G1[0] R0[1] B1[2] R0[0] B1[1] G0[1] B1[0]
D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
P0a G0[3] G0[2] G0[1] G0[0] B0[7] B0[6] B0[5] B0[4] B0[3] B0[2] B0[1] B0[0]
P1b R1[7] R1[6] R1[5] R1[4] R1[3] R1[2] R1[1] R1[0] G1[7] G1[6] G1[5] G1[4]
P0a G0[4] G0[3] G0[2] B0[7] B0[6] B0[5] B0[4] B0[3] G0[0] B0[2] B0[1] B0[0]
P1b R1[7] R1[6] R1[5] R1[4] R1[3] G1[7] G1[6] G1[5] R1[2] R1[1] R1[0] G1[1]
Table 5. YCrCb Multiplexed Mode
IDF# Format Pixel# Bus Data 9 YCrCb 8-bit P1b P2a Y1[7] Cb2[7] Y1[6] Cb2[6] Y1[5] Cb2[5] Y1[4] Cb2[4] Y1[3] Cb2[3] Y1[2] Cb2[2] Y1[1] Cb2[1] Y1[0] Cb2[0]
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
P0a Cb0[7] Cb0[6] Cb0[5] Cb0[4] Cb0[3] Cb0[2] Cb0[1] Cb0[0]
P0b Y0[7] Y0[6] Y0[5] Y0[4] Y0[3] Y0[2] Y0[1] Y0[0]
P1a Cr0[7] Cr0[6] Cr0[5] Cr0[4] Cr0[3] Cr0[2] Cr0[1] Cr0[0]
P2b Y2[7] Y2[6] Y2[5] Y2[4] Y2[3] Y2[2] Y2[1] Y2[0]
P3a Cr2[7] Cr2[6] Cr2[5] Cr2[4] Cr2[3] Cr2[2] Cr2[1] Cr2[0]
P3b Y3[7] Y3[6] Y3[5] Y3[4] Y3[3] Y3[2] Y3[1] Y3[0]
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CH7007A
When IDF = 9, (YCrCb 8-bit mode), H and V sync signals can be embedded into the data stream. In this mode, the embedded sync will be similar to the CCIR656 convention, and the first byte of the `video timing reference code' will be assumed to occur when a Cb sample would occur - if the video stream was continuous. This is delineated in Table 6 shown below. Table 6. YCrCb Multiplexed Mode with Embedded Syncs
IDF# Format Pixel# Bus Data D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] P0a 1 1 1 1 1 1 1 1 P0b 0 0 0 0 0 0 0 0 P1a 0 0 0 0 0 0 0 0 9 YCrCb 8-bit P1b S[7] S[6] S[5] S[4] S[3] S[2] S[1] S[0] P2a Cb2[7] Cb2[6] Cb2[5] Cb2[4] Cb2[3] Cb2[2] Cb2[1] Cb2[0] P2b Y2[7] Y2[6] Y2[5] Y2[4] Y2[3] Y2[2] Y2[1] Y2[0] P3a Cr2[7] Cr2[6] Cr2[5] Cr2[4] Cr2[3] Cr2[2] Cr2[1] Cr2[0] P3b Y3[7] Y3[6] Y3[5] Y3[4] Y3[3] Y3[2] Y3[1] Y3[0]
In this mode, the S[7:0] byte contains the following data: S[6] S[5] S[4] = = = F V H = = = 1 during field 2, 0 during field 1 1 during field blanking, 0 elsewhere 1 during EAV (the synchronization reference at the end of active video) 0 during SAV (the synchronization reference at the start of active video)
Bits S[7] and S[3-0] are ignored.
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Functional Description
CH7007A
The CH7007 is a TV-output companion chip to graphics controllers providing digital output in either YCrCb or RGB format. This solution involves both hardware and software elements which work together to produce an optimum TV screen image based on the original computer generated pixel data. All essential circuitry for this conversion are integrated on chip. On chip circuitry includes memory, memory control, scaling, PLL, DAC, filters and NTSC/PAL encoder. All internal signal processing, including NTSC/PAL encoding, is performed using digital techniques to ensure that the high-quality video signals are not affected by drift issues associated with analog components. No additional adjustment is required during manufacturing. CH7007 is ideal for PC motherboards, web browsers or VGA add-in boards where a minimum of discrete support components (passive components, parallel resonance 14.31818 MHz crystal) are required for full operation.
Architectural Overview
The CH7007 is a complete TV output subsystem which uses both hardware and software elements to produce an image on TV which is virtually identical to the image that would be displayed on a monitor. Simply creating a compatible TV output from a VGA input involves a relatively straightforward process. This process includes a standard conversion from RGB to YUV color space, converting from a non-interlaced to an interlaced frame sequence, and encoding the pixel stream into NTSC or PAL compliant format. However, creating an optimum computer-generated image on a TV screen involves a highly sophisticated process of scaling, deflickering, and filtering. This results in a compatible TV output that displays a sharp and subtle image, of the right size, with minimal artifacts from the conversion process. As a key part of the overall system solution, the CH7007 software establishes the correct framework for the VGA input signal to enable this process. Once the display is set to a supported resolution (either 640x480 or 800x600), the CH7007 software may be invoked to establish the appropriate TV output display. The software then programs the various timing parameters of the VGA controller to create an output signal that will be compatible with the chosen resolution, operating mode, and TV format. Adjustments performed in software include pixel clock rates, total pixels per line, and total lines per frame. By performing these adjustments in software, the CH7007 can render a superior TV image without the added cost of a full frame buffer memory - normally used to implement features such as scaling and full synchronization. The CH7007 hardware accepts digital RGB or YCrCb inputs, which are latched in synchronization with the pixel clock. These inputs are then color-space converted into YUV in 4-2-2 format, and stored in a line buffer memory. The stored pixels are fed into a block where scan-rate conversion, underscan scaling and 2-line, 3-line, 4-line or 5line vertical flicker filtering are performed. The scan-rate converter transforms the VGA horizontal scan-rate to either NTSC or PAL scan rates; the vertical flicker filter eliminates flicker at the output while the underscan scaling reduces the size of the displayed image to fit onto a TV screen. The resulting YUV signals are filtered through digital filters to minimize aliasing problems. The digital encoder receives the filtered signals and transforms them to composite and S-Video outputs, which are converted by the three 9-bit DACs into analog outputs.
Color Burst Generation*
The CH7007 allows the subcarrier frequency to be accurately generated from a 14.31818 MHz crystal oscillator, leaving the subcarrier frequency independent of the sampling rate. As a result, the CH7007 may be used with any VGA chip (with an appropriate digital interface) since the CH7007 subcarrier frequency can be generated without being dependent on the precise pixel rates of VGA controllers. This feature is a significant benefit, since even a 0.01% subcarrier frequency variation may be enough to cause some television monitors to lose color lock. In addition, the CH7007 has the capability to genlock the color burst signal to the VGA horizontal sync frequency, which enables a fully synchronous system between the graphics controller and the television. When genlocked, the CH7007 can also stop "dot crawl" motion (for composite mode operation in NTSC modes) to eliminate the annoyance of moving borders. Both of these features are under programmable control through the register set.
Display Modes
The CH7007 display mode is controlled by three independent factors: input resolution, TV format, and scale factor, which are programmed via the display mode register. It is designed to accept input resolutions of 640x480, 800x600, 640x400 (including 320x200 scan-doubled output), 720x400 and 512x384.
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* Patent number 5,874,846
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CHRONTEL
Display Modes (continued)
CH7007A
It is designed to support output to either NTSC or PAL television formats. The CH7007 provides interpolated scaling with selectable factors of 5:4, 1:1, 7:8, 5:6, 3:4 and 7:10 in order to support adjustable overscan or underscan operation when displayed on a TV. This combination of factors results in a matrix of useful operating modes which are listed in detail in Table 7. Table 7. CH7007 Display Modes
TV Format Standard NTSC NTSC NTSC NTSC NTSC NTSC NTSC NTSC NTSC NTSC NTSC NTSC NTSC PAL PAL PAL PAL PAL PAL PAL PAL PAL PAL PAL PAL Input (active) Resolution
640x480 640x480 640x480 800x600 800x600 800x600 640x400 640x400 640x400 720x400 720x400 512x384 512x384 640x480 640x480 640x480 800x600 800x600 800x600 640x400 640x400 720x400 720x400 512x384 512x384
Scale Factor
1:1 7:8 5:6 5:6 3:4 7:10 5:4 1:1 7:8 5:4 1:1 5:4 1:1 5:4 1:1 5:6 1:1 5:6 3:4 5:4 1:1 5:4 1:1 5:4 1:1
Active TV Lines
480 420 400 500 450 420 500 400 350 500 400 480 384 600 480 400 600 500 450 500 400 500 400 480 384
Percent (1) Overscan
10% (3%) (8%) 16% 4% (3%) 16% (8%) (19%) 16% (8%) 10% (11%) 14% (8%) (29%) 14% (4%) (15%) (4%) (29%) (4%) (29%) (8%) (35%)
Pixel Clock
24.671 28.196 30.210 39.273 43.636 47.832 21.147 26.434 30.210 23.790 29.455 20.140 24.671 21.000 26.250 31.500 29.500 36.000 39.000 25.000 31.500 28.125 34.875 21.000 26.250
Horizontal Total
784 784 800 1040 1040 1064 840 840 840 945 936 800 784 840 840 840 944 960 936 1000 1008 1125 1116 840 840
Vertical Total
525 600 630 630 700 750 420 525 600 420 525 420 525 500 625 750 625 750 836 500 625 500 625 500 625
(1) Note: Percent underscan is a calculated value based on average viewable lines on each TV format, assuming an average TV overscan of 10%. (Negative values) indicate modes which are operating in underscan. For NTSC: 480 active lines - 10% (overscan) = 432 viewable lines (average) For PAL: 576 active lines - 10% (overscan) = 518 viewable lines (average)
The inclusion of multiple levels of scaling for each resolution have been created to enable optimal use of the CH7007 for different application needs. In general, underscan (modes where percent overscan is negative) provides an image that is viewable in its entirety on screen; it should be used as the default for most applications (e.g., viewing text screens, operating games, running productivity applications and working within Windows). Overscanning provides an image that extends past the edges of the TV screen, exactly like normal television programs and movies appear on TV, and is only recommended for viewing movies or video clips coming from the computer. In addition to the above mode table, the CH7007 also support interlaced input modes, both in CCIR 656 and proprietary formats (see Display Mode Register section). Flicker Filter and Text Enhancement The CH7007 integrates an advanced 2-line, 3-line, 4-line and 5-line (depending on mode) vertical deflickering filter circuit to help eliminate the flicker associated with interlaced displays. This flicker circuit provides an adaptive filter algorithm for implementing flicker reduction with selections of high, medium or low flicker content for both luma and chroma channels (see register descriptions). In addition, a special text enhancement circuit incorporates
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CHRONTEL
Display Modes (continued)
CH7007A
additional filtering for enhancing the readability of text. These modes are fully programmable via I2C under the flicker filter register.
Internal Voltage Reference
An on chip bandgap circuit is used in the DAC to generate a reference voltage which, in conjunction with a reference resistor at pin ISET, and register controlled divider, sets the output ranges of the DACs. The CH7007 bandgap reference voltage is 1.235 volts nominal for NTSC or PAL-M, or 1.317 volts nominal for PAL or NTSC-J, which is determined by IDF register bit 6 (DACG bit). The recommended value for the reference resistor from ISET to ground is 360 ohms (though this may be adjusted in order to achieve a different output level). The gain setting for DAC output is 1/48th . Therefore, for each DAC, the current output per LSB step is determined by the following equation: ILSB = V(ISET)/ISET reference resistor * 1/GAIN For DACG=0, this is: I LSB = 1.235/360 * 1/48 = 71.4 A (nominal) For DACG=1, this is: I LSB = 1.317/360 * 1/48 = 76.2 A (nominal)
Power Management
The CH7007 supports five operating states including Normal [On], Power Down, Full Power Down, S-Video Off and Composite Off to provide optimal power consumption for the application involved. Using the programmable power down modes accessed over the I 2C port, the CH7007 may be placed in either Normal state, or any of the four power managed states, as listed below (see "Power Management Register" under theRegister Descriptions section for programming information). To support power management, a TV sensing function (see "Connection Detect Register" under the Register Descriptions section) is provided, which identifies whether a TV is connected to either S-Video or composite. This sensing function can then be used to enter into the appropriate operating state (e.g., if TV is sensed only on composite, the S-Video Off mode could be set by software). Table 8. Power Management
Operating State
Normal (On): Power Down:
Functional Description
In the normal operating state, all functions and pins are active. In the power-down state, most pins and circuitry are disabled.The DS/BCO pin will continue to provide either the VCO divided by K3, or 14.318 MHz out when selected as an output, and the P-OUT pin will continue to output a clock reference when in master clock mode. Power is shut off to the unused DACs associated with S-Video outputs. In Composite-off state, power is shut off to the unused DAC associated with CVBS output. In this power-down state, all but the I 2C circuits are disabled. This places the CH7007 in its lowest power consumption mode.
S-Video Off: Composite Off: Full Power Down:
Luminance and Chrominance Filter Options
The CH7007 contains a set of luminance filters to provide a controllable bandwidth output on both CVBS and SVideo outputs. All values are completely programmable via the Video Bandwidth Register. For all graphs shown, the horizontal axis is frequency in MHz, and the vertical axis is attenuation in dBs. The composite luminance and chrominance video bandwidth output is shown in Table 9.
MacrovisionTM Anti-copy Protection
The CH7007 implements the Macrovision 7.X anti-copy protection process. This process changes the encoded output of the NTSC/PAL signals to inhibit recording on VCR devices while not affecting viewing on a TV. The parameters that control this process are fully programmable and can be described by Chrontel only after a suitable Non-Disclosure Agreement has been executed between MacrovisionTM , Inc. and the customer.
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CHRONTEL
CH7007A
Table 9. Video Bandwidth
Mode Chrominance CBW[1:0]
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 00 0.62 0.78 0.53 0.65 0.83 1.03 0.70 0.87 0.74 0.93 0.63 0.78 0.89 0.62 0.78 0.93 0.64 0.74 0.79 0.77 0.95 1.02 0.77 0.86 0.94 0.71 0.71 01 0.68 0.85 0.58 0.71 0.91 1.13 0.77 0.95 0.81 1.02 0.68 0.86 0.98 0.68 0.85 1.02 0.71 0.81 0.87 0.85 1.03 1.12 0.85 0.94 1.03 0.78 0.78 10 0.80 1.00 0.68 0.83 1.07 1.32 0.90 1.12 0.95 1.20 0.80 1.00 1.15 0.80 1.00 1.20 0.83 0.95 1.02 1.00 1.22 1.32 0.99 1.11 1.21 0.91 0.91 11 0.95 1.18 0.81 0.99 1.27 1.57 1.07 1.33 1.13 1.42 0.95 1.19 1.36 0.95 1.18 1.42 0.98 1.13 1.21 1.18 1.44 1.56 1.18 1.31 1.44 1.08 1.08
0
CVBS YCV 1
3.37 4.21 2.87 3.52 4.51 5.59 3.81 4.72 4.01 5.05 3.39 4.24 4.84 3.37 4.21 5.05 3.50 4.02 4.31 4.20 5.13 5.56 4.20 4.66 5.11 3.85 3.85
Luminance Bandwidth S-Video YSV[1:0], YPEAK = 0
00 2.26 2.82 1.93 2.36 3.03 3.75 2.56 3.17 2.69 3.39 2.28 2.84 3.25 2.26 2.82 3.39 2.35 2.70 2.89 2.82 3.44 3.73 2.82 3.13 3.43 2.58 2.58 01 3.37 4.21 2.87 3.52 4.51 5.59 3.81 4.72 4.01 5.05 3.39 4.24 4.84 3.37 4.21 5.05 3.50 4.02 4.31 4.20 5.13 5.56 4.20 4.66 5.11 3.85 3.85 1X 5.23 6.53 4.46 5.46 7.00 8.68 5.92 7.33 6.22 7.84 5.26 6.58 7.52 5.23 6.53 7.84 5.43 6.24 6.68 6.53 7.97 8.63 6.52 7.24 7.94 5.97 5.97
with
Sin(X) /X (MHz) S-Video YSV[1:0], YPEAK = 1
00 2.57 3.21 2.19 2.68 3.44 4.27 2.91 3.60 3.06 3.85 2.59 3.23 3.70 2.57 3.21 3.85 2.67 3.07 3.29 3.21 3.92 4.24 3.20 3.56 3.90 2.94 2.94 01 4.44 5.56 3.79 4.64 5.95 7.38 5.04 6.23 5.29 6.67 4.48 5.59 6.39 4.44 5.56 6.67 4.62 5.30 5.68 5.55 6.77 7.34 5.54 6.16 6.75 5.08 5.08 1X 5.23 6.53 4.46 5.46 7.00 8.68 5.92 7.33 6.22 7.84 5.26 6.58 7.52 5.23 6.53 7.84 5.43 6.24 6.68 6.53 7.97 8.63 6.52 7.24 7.94 5.97 5.97
2.26 2.82 1.93 2.36 3.03 3.75 2.56 3.17 2.69 3.39 2.28 2.84 3.25 2.26 2.82 3.39 2.35 2.70 2.89 2.82 3.44 3.73 2.82 3.13 3.43 2.58 2.58
The composite luminance and chrominance frequency response is depicted in Figures 5 through 7.
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CHRONTEL
Luminance and Chrominance Filter Options (continued)
0 0
CH7007A
-66
-12 12 -18 18
(YCVdB YCVdB
< i>

nn
)
-24 24 -30 30 -36 36 -42 42
0
0
1
1
2 2
3 3
4 4
5 5
fn,i
f
6 6 n, i
7 7
8 8
9 9
10 10
11 11
12
12
106 10 6
Figure 5: Composite Luminance Frequency Response (YCV = 0) 0
-6 -12
-18
(YSVdB
>
)n
-24 -30 -36 -42 0
1
2
3
4
5
6
fn , i 1 06
7
8
9
10
11
12
Figure 6: S-Video Luminance Frequency Response (YSV = 1X, YPEAK = 0)
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CHRONTEL
Luminance and Chrominance Filter Options (continued)
CH7007A
0 0
-6 6
-12 12
18 -18
(UVfirdB)n
24 -24
UVfirdB n
30 -30
36 -36
-42 0 42 0
1 1
2 2
3 3
4 4
5 5
6 6 f f n,i , i n
7 7
8 8
9 9
10 10
11 11
12 12
10 66 10
Figure 7: Chrominance Frequency Response
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CHRONTEL
NTSC and PAL Operation
CH7007A
Composite and S-Video outputs are supported in either NTSC or PAL format. The general parameters used to characterize these outputs are listed in Table10 and shown in Figure8 (See Figures 11 through 16 for illustrations . of composite and S-Video output waveforms).
CCIR624-3 Compliance
The CH7007 is predominantly compliant with the recommendations called out in CCIR624-3. The following are the only exceptions to this compliance: * The frequencies of Fsc, Fh, and Fv can only be guaranteed in master mode, not in slave mode when the graphics device generates these frequencies. * It is assumed that gamma correction, if required, is performed in the graphics device which establishes the color reference signals. * All modes provide the exact number of lines called out for NTSC and PAL modes respectively, except mode 21, which outputs 800x600 resolution, scaled by 3:4, to PAL format with a total of 627 lines (vs. 625). * Chroma signal frequency response will fall within 10% of the exact recommended value. * Pulse widths and rise/fall times for sync pulses, front/back porches, and equalizing pulses are designed to approximate CCIR624-3 requirements, but will fall into a range of values due to the variety of clock frequencies used to support multiple operating modes. Table 10. NTSC/PAL Composite Output Timing Parameters (in mS)
Symbol Description NTSC
A B C D E F G H Front Porch Horizontal Sync Breezeway Color Burst Back Porch Black Active Video Black 287 0 287 287 287 340 340 340
Level (mV) PAL
300 0 300 300 300 300 300 300
Duration (uS) NTSC
1.49 - 1.51 4.69 - 4.72 0.59 - 0.61 2.50 - 2.53 1.55 - 1.61 0.00 - 7.50 37.66 - 52.67 0.00 - 7.50
PAL
1.48 - 1.51 4.69 - 4.71 0.88 - 0.92 2.24 - 2.26 2.62 - 2.71 0.00 - 8.67 34.68 - 52.01 0.00 - 8.67
For this table and all subsequent figures, key values are:
Note: 1. 2. 3. 4. ISET = 360 ohms; V(ISET) = 1.235V; 75 ohms doubly terminated load. Durations vary slightly in different modes due to the different clock frequencies used. Active video and black (F, G, H) times vary greatly due to different scaling ratios used in different modes. Black times (F and H) vary with position controls.
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CHRONTEL
CH7007A
A
B
C
D
E
F
G
H
Figure 8: NTSC / PAL Composite Output
START START OF O F VSYNC VSYNC ANALOG StartANALOG of fieldFIELD 1 1 FIELD 1
523 520 520
524 521 521
525 522 522
523 523 1
524 524 2
3 525 525
14 1
2 2 5
36 3
47 4
58 5
69 6
10 7 7
11 8 8
12 9 9
Pre-equalizing pulse interval
Vertical sync pulse interval
Post-equalizing pulse interval
Reference Line ANALOG ANALOG vertical sub-carrier phase FIELD 1 FIELD 2 t 1+V interval color field 2
261 258 258
262 259 259
263 260 260
264 261 261 Start of field 2
265 262 262
266 263 263
267 264 264
268 265 265
269 266 266
270 267 267
271 268 268
272 269 269
273 270 270
274 271 271
275 272 272
START O F VSYNC
Reference ANALOG sub-carrier phase FIELD 1 t 2+V color field 2
523 520
524 521
522 525
523 1 Start of field 3
2 524
525 3
1 4
2 5
6 3
7 4
8 5
9 6
10 7
11 8
12 9
Reference ANALOG sub-carrier phase FIELD 2 color field 3
t 3+V
261 258
262 259
263 260
264 261 Start of field 4
262 265
263 266
264 267
265 268
269 266
270 267
268 271
269 272
273 270
274 271
272 275
Reference sub-carrier phase color field 4
Figure 9: Interlaced NTSC Video Timing
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CHRONTEL
START START OF F O VSYNC VSYNC
CH7007A
ANALOG ANALOG FIELD 1 FIELD 1
620 620
621 621
622 622
623 623
624 624
625 625
1 1
2 2
3 3
4 4
5 5
6 6
7 7
8 8
9 9
10 10
ANALOG ANALOG FIELD 2 FIELD 2
308 308
309 309
310 310
311 311
312
313 313
314
315
316 316
317
318 318
319 319
320 320
321 321
322 322
323 323
ANALOG ANALOG FIELD 3 FIELD 3
620 620
621 621
622 622
623 623
624 624
625 625
1
2 2
3
4
5 5
6
7 7
8 8
9 9
10 10
ANALOG ANALOG FIELD 4 FIELD 4
308 308
309 309
310 310
311 311
312
313 313
314
315
316 316
317
318 318
319 319
320 320
321 321
322 322
323 323
BURST BURST BLANKING BLANKING INTERVALS
4 3 BURST RELATIVE TO U BURST PHASE = REFERENCE PHASE = 135 RELATIVE TO U PAL SWITCH = 0, +V COMPONENT PAL SWITCH = 0, +V COMPONENT 2 1 BURST PHASE = REFERENCE PHASE + 90= 225 RELATIVE TO U BURST PHASE = REFERENCE PHASE + 90= 225 RELATIVE TO U PAL PAL SWITCH = 1, - V COMPONENT
Figure 10: Interlaced PAL Video Timing
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CHRONTEL
CH7007A
Magenta
Green Cyan Yellow
White
Black
Color/Level White Yellow
mA 26.66 24.66
V 1.000 0.925
Color bars:
Blue Red
Cyan Green Magenta Red
21.37 19.37 16.22 14.22
0.801 0.726 0.608 0.533
Blue Black Blank
11.08 9.08 7.65
0.415 0.340 0.287
Sync
0.00
0.000
Figure 11: NTSC Y (Luminance) Output Waveform (DACG = 0)
Blue Red Magenta
Green Cyan Yellow
White
Black
Color/Level White Yellow
mA 26.75 24.62
V 1.003 0.923
Color bars:
Cyan Green Magenta Red
21.11 18.98 15.62 13.49
0.792 0.712 0.586 0.506
Blue Blank/ Black
10.14 8.00
0.380 0.300
Sync
0.00
0.000
Figure 12: PAL Y (Luminance) Video Output Waveform (DACG = 1)
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CHRONTEL
CH7007A
Magenta
Yellow
W hite
G reen
Black
Cyan
Color bars:
Color/Level Cyan/Red Green/Magenta mA 25.80 25.01 V 0.968 0.938
Blue
Red
Yellow/Blue
22.44
0.842
Peak Burst Blank Peak Burst
18.08 14.29 10.51
0.678 0.536 0.394
3.579545 MHz Color Burst (9 cycles)
Yellow/Blue
6.15
0.230
Green/Magenta Cyan/Red
3.57 2.79
0.134 0.105
Figure 13: NTSC C (Chrominance) Video Output Waveform (DACG = 0)
Magenta
Yellow
White
Green
Black
Cyan
Color bars:
Color/Level Cyan/Red Green/Magenta mA 27.51 26.68 V 1.032 1.000
Blue
Red
Yellow/Blue
23.93
0.897
Peak Burst Blank Peak Burst
19.21 15.24 11.28
0.720 0.572 0.423
4.433619 MHz Color Burst (10 cycles)
Yellow/Blue
6.56
0.246
Green/Magenta Cyan/Red
3.81 2.97
0.143 0.111
Figure 14: PAL C (Chrominance) Video Output Waveform (DACG = 1)
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CHRONTEL
CH7007A
Magenta
Yellow
Gr een
White
Black
Cyan
Blue
Red
Color/Level Peak Chrome White
mA 32.88 26.66
V 1.233 1.000
Color bars:
Peak Burst Black Blank
11.44 9.08 7.65
0.429 0.340 0.281
Peak Burst
4.45
0.145
3.579545 MHz Color Burst (9 cycles)
Sync 0.00 0.000
Figure 15: Composite NTSC Video Output Waveform (DACG = 0)
Magenta
Yellow
G reen
White
Black
Cyan
Blue
Red
Color/Level
mA
V 1.249 1.003
Color bars:
Peak Chrome 33.31 White 26.75
Peak Burst
11.97
0.449
Blank/Black
8.00
0.300
Peak Burst
4.04
0.151
Sync
0.00
0.000
4.433619 MHz Color Burst (10 cycles)
Figure 16: Composite PAL Video Output Waveform (DACG = 1)
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CHRONTEL
I2C Port Operation
CH7007A
The CH7007 contains a standard I2C control port, through which the control registers can be written and read. This port is comprised of a two-wire serial interface, pins SD (bidirectional) and SC, which can be connected directly to the SDB and SCB buses as shown in Figure17. The Serial Clock line (SC) is input only and is driven by the output buffer of the master device (also shown in Figure17). The CH7007 acts as a slave, and generation of clock signals on the bus is always the responsibility of the master device. When the bus is free, both lines are HIGH. The output stages of devices connected to the bus must have an open-drain or open-collector to perform the wired-AND function. Data on the bus can be transferred up to 400 kbit/s.
+DVDD RP
SDB (Serial Data Bus) SCB (Serial Clock Bus) SC DATAN2 OUT MASTER SCLK OUT FROM MASTER SD
DATAN2 OUT
DATAN2 OUT
DATA IN MASTER BUS MASTER
SCLK IN1 SLAVE
DATA IN1
SCLK IN2 SLAVE
DATA IN2
Figure 17: Connection of Devices to the Bus
Electrical Characteristics for Bus Devices
The electrical specifications of the bus devices' inputs and outputs and the characteristics of the bus lines connected to them are shown in Figure17. A pull-up resistor (RP ) must be connected to a 3.3V 10% supply. The CH7007 is a device with input levels related to DVDD. Maximum and minimum values of pull-up resistor (R P) The value of RP depends on the following parameters: * Supply voltage * Bus capacitance * Number of devices connected (input current + leakage current = I input) The supply voltage limits the minimum value of resistor RP due to the specified minimum sink current of 2mA at VOL max = 0.4 V for the output stages: RP >= (VDD - 0.4) / 2 (R P in k) The bus capacitance is the total capacitance of wire, connections and pins. This capacitance limits the maximum value of RP due to the specified rise time. The equation for RP is shown below: RP <= 103 /C (where: RP is in k and C, the total capacitance, is in pF) The maximum HIGH level input current of each input/output connection has a specified maximum value of 10 A. Due to the desired noise margin of 0.2V DD for the HIGH level, this input current limits the maximum value of RP. The R P limit depends on VDD and is shown below: RP <= (100 x VDD)/ I input (where: R P is in k and I input is in A)
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CHRONTEL
Transfer Protocol
CH7007A
Both read and write cycles can be executed in "Alternating" and "Auto-increment" modes. Alternating mode expects a register address prior to each read or write from that location (i.e., transfers alternate between address and data). Auto-increment mode allows you to establish the initial register location, then automatically increments the register address after each subsequent data access (i.e., transfers will be address, data...). A basic serial port transfer protocol is shown in Figure18 and described below.
SD
I2 C
SC
CH7007
8
9
1-8
9
1-8
9
Start Condition
Device ID
R/W*
ACK
CH7007 acknowledge
Data1
ACK
CH7007 acknowledge
Data n
CH7007 acknowledge
ACK
Stop Condition
Figure 18: Serial Port Transfer Protocol 1. The transfer sequence is initiated when a high-to-low transition of SD occurs while SC is high; this is the "START" condition. Transitions of address and data bits can only occur while SC is low. 2. The transfer sequence is terminated when a low-to-high transition of SD occurs while SC is high; this is the "STOP" condition. 3. Upon receiving the first START condition, the CH7007 expects a Device Address Byte (DAB) from the master device. The value of the device address is shown in the DAB data format below. 4. After the DAB is received, the CH7007 expects a Register Address Byte (RAB) from the master. The format of the RAB is shown in the RAB data format below (note that B7 is not used).
Device Address Byte (DAB)
B7
1
B6
1
B5
1
B4
0
B3
1
B2
0
B1
1
B0
R/W
R/W
Read/Write Indicator
"0": "1":
master device will write to the CH7007 at the register location specified by the address AR[5:0] master device will read from the CH7007 at the register location specified by the address AR[5:0].
Register Address Byte (RAB)
B0
AR[0]
B7
1
B6
AutoInc
B5
AR[5]
B4
AR[4]
B3
AR[3]
B2
AR[2]
B1
AR[1]
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CHRONTEL
Transfer Protocols (continued)
AutoInc
CH7007A
Register Address Auto-Increment - to facilitate sequential R/W of registers.
"1":
Auto-Increment enabled (auto-increment mode).
Write: After writing data into a register, the Address Register will automatically be incremented by one. Read: Before loading data from a register to the on-chip temporary register (getting ready to be serially read), the Address Register will automatically be incremented by one. However, for the first read after an RAB, the Address Register will not be changed. "0": Auto-Increment disabled (alternating mode).
Write: After writing data into a register, the Address Register will remain unchanged until a new RAB is written. Read: Before loading data from a register to the on-chip temporary register (getting ready to be serially read), the Address Register will remain unchanged.
AR[5:0] Specifies the Address of the Register to be Accessed.
This register address is loaded into the Address Register of the CH7007. The R/W access, which follows, is directed to the register specified by the content stored in the Address Register. The following two sections describe the operation of the serial interface for the four combinations of R/W = 0,1 and AutoInc = 0,1.
CH7007 Write Cycle Protocols (R/W = 0)
Data transfer with acknowledge is required. The acknowledge-related clock pulse is generated by the mastertransmitter. The master-transmitter releases the SD line (HIGH) during the acknowledge clock pulse. The slavereceiver must pull down the SD line, during the acknowledge clock pulse, so that it remains stable LOW during the HIGH period of the clock pulse. The CH7007 always acknowledges for writes (see Figure19). Note that the resultant state on SD is the wired-AND of data outputs from the transmitter and receiver.
SD Data Output By Master-Transmitter SD Data Output By the CH7007 SC from Master Start Condition 1 2
not acknowledge
acknowledge 8 9
clock pulse for acknowledgment
Figure 19: Acknowledge on the Bus
Figure 20 shows two consecutive alternating write cycles for AutoInc = 0 and R/W = 0. The byte of information, following the Register Address Byte (RAB), is the data to be written into the register specified by AR[5:0]. If AutoInc = 0, then another RAB is expected from the master device, followed by another data byte, and so on.
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CHRONTEL
CH7007A
SD
CH7007 acknowledge
CH7007 acknowledge
CH7007 acknowledge
CH7007 acknowledge
CH7007 acknowledge
I2 C
SC
1-7
8
9
1-8
9
1-8
9
1-8
9
1-8
9
Start Condition
Device ID
R/W*
ACK
RAB
ACK
Data
ACK
RAB
ACK
Data
ACK
Stop Condition
Note: The acknowledge is from the CH7007 (slave).
Figure 20: Alternating Write Cycles If AutoInc = 1, then the register address pointer will be incremented automatically and subsequent data bytes will be written into successive registers without providing an RAB between each data byte. An Auto-increment write cycle is shown in Figure21. .
CH7007 acknowledge CH7007 acknowledge CH7007 acknowledge CH7007 acknowledge
SD
I2 C
SC
1-7
8
9
1-8
9
1-8
9
1-8
9
Start Condition
Device ID
R/W*
ACK
RAB n
ACK
Data n
ACK
Data n+1
ACK
Stop Condition
Note: The acknowledge is from the CH7007 (slave).
Figure 21: Auto-Increment Write Cycle When the auto-increment mode is enabled (AutoInc is set to 1), the register address pointer continues to increment for each write cycle until AR[5:0] = 3F (3F is the address of the Address Register). The next byte of information represents a new auto-sequencing "Starting address", which is the address of the register to receive the next byte. The auto-sequencing then resumes based on this new "Starting address". The auto-increment sequence can be terminated any time by either a "STOP" or "RESTART" condition. The write operation can be terminated with a "STOP" condition.
CH7007 Read Cycle Protocols (R/W = 1)
If a master-receiver is involved in a transfer, it must signal the end of data to the slave-transmitter by not generating an acknowledge on the last byte that was clocked out of the slave. The slave-transmitter CH7007 releases the data line to allow the master to generate the STOP condition or the RESTART condition. To read the content of the registers, the master device starts by issuing a "START" condition (or a "RESTART" condition). The first byte of data, after the START condition, is a DAB with R/W = 0. The second byte is the RAB with AR[5:0], containing the address of the register that the master device intends to read from in AR[5:0]. The master device should then issue a "RESTART" condition ("RESTART" = "START", without a previous "STOP" condition). The first byte of data, after this RESTART condition, is another DAB with R/W=1, indicating the master's intention to read data hereafter. The master then reads the next byte of data (the content of the register specified in the RAB). If AutoInc = 0, then another RESTART condition, followed by another DAB with R/W = 0 and RAB, is expected from the master device. The master device then issues another RESTART, followed by another DAB. After that, the master may read another data byte, and so on. In summary, a RESTART condition, followed by a DAB, must be produced by the master before each of the RAB, and before each of the data read events. Two consecutive alternating read cycles are shown in Figure22.
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Transfer Protocols (continued)
.
CH7007 acknowledge CH7007 acknowledge CH7007 acknowledge
CH7007A
SD
Master does not acknowledge
I 2C
I2 C
SC Start Condition
1-7
8
9
1-8
9
10
1-7
8
9
1-8
9
10
Device ID R/W*
ACK
RAB 1
ACK
Restart Condition
Device ID R/W*
ACK
Data 1
ACK
Restart Condition
Master does not acknowledge CH7007 acknowledge CH7007 acknowledge CH7007 acknowledge
I2 C
I2 C
1-7
8
9
1-8
9
10
1-7
8
9
1-8
9
Device ID
R/W*
ACK
RAB 2
ACK
Restart Device ID Condition
R/W*
ACK
Data 2
ACK
Stop Condition
Figure 22: Alternating Read Cycle If AutoInc = 1, then the address register will be incremented automatically and subsequent data bytes can be read from successive registers, without providing a second RAB.
CH7007 acknowledge
CH7007 acknowledge
CH7007 acknowledge
Master acknowledge
Master does not acknowledge just before Stop condition
SD
I 2C
SC
1-7
8
9
1-8
9
10
1-7
8
9
1-8
9
1-8
9
Start Device ID R/W* Condition
ACK
RAB n
ACK
Restart Device ID R/W* Condition
ACK
Data n
ACK
Data n+1
ACK
Stop Condition
Figure 23: Auto-increment Read Cycle When the auto-increment mode is enabled (AutoInc is set to 1), the Address Register will continue incrementing for each read cycle. When the content of the Address Register reaches 2A, it will wrap around and start from 00h again. The auto increment sequence can be terminated by either a "STOP" or "RESTART" condition. The read operation can be terminated with a "STOP" condition. Figure23 shows an auto-increment read cycle terminated by a STOP or RESTART condition.
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Registers and Programming
CH7007A
The CH7007 is a fully programmable device, providing for full functional control through a set of registers accessed from the I2C port. The CH7007 contains a total of 37 registers, which are listed in Table 11 and described in detail under Register Descriptions. Detailed descriptions of operating modes and their effects are contained in the previous section, Functional Description. An addition (+) sign in the Bits column below signifies that the parameter contains more than 8 bits, and the remaining bits are located in another register. Table 11. Register Map
Register
Display Mode Flicker Filter Video Bandwidth Input Data Format Clock Mode Start Active Video Position Overflow Black Level Horizontal Position Vertical Position Sync Polarity Power Management Connection Detect Contrast Enhancement PLL M and N extra bits PLL-M Value PLL-N Value Buffered Clock Subcarrier Frequency Adjust PLL and Memory Control CIV Control Calculated Fsc Increment Value Version ID Test Address
Symbol
DMR FFR VBW IDF CM SAV PO BLR HPR VPR SPR PMR CDR CE MNE PLLM PLLN BCO FSCI PLLC CIVC CIV VID TR AR
Address
00H 01H 03H 04H 06H 07H 08H 09H 0AH 0BH 0DH 0EH 10H 11H 13H 14H 15H 17H 18H -1FH 20H 21H 21H 24H 25H 26H 29H 3FH
Bits
8 6 8 6 8 8+ 3 8 8+ 8+ 4 5 4 3 5 8+ 8+ 6 4 or 8 each 6 5 8 each 8 30 6
Functional Summary
Display mode selection Flicker filter mode selection Luma and chroma filter bandwidth selection Data format and bit-width selections Sets the clock mode to be used Active video delay setting MSB bits of position values Black level adjustment input latch clock edge select Enables horizontal movement of displayed image on TV Enables vertical movement of displayed image on TV Determines the horizontal and vertical sync polarity Enables power saving modes Detection of TV presence Contrast enhancement setting Contains the MSB bits for the M and N PLL values Sets the PLL M value - bits (7:0) Sets the PLL N value - bits (7:0) Determines the clock output at pin 41 Determines the subcarrier frequency Controls for the PLL and memory sections Control of CIV value Readable register containing the calculated subcarrier increment value Device version number Reserved for test (details not included herein) Current register being addressed
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Register Descriptions (continued)
CH7007A
Table 12. I2 C Alternate Register Map (Note: Macrovision T M controls available only by special arrangement)
Register
00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 3FH YLM7 CLM7 Reserved YLM6 CLM6 Reserved CIV23 CIV15 CIV7 VID7 TS3 CIV22 CIV14 CIV6 VID6 TS2 CIV21 CIV13 CIV5 VID5 TS1 MS2 YLM5 CLM5 AR5 PLLCPl PLLCAP CIV25 CIV20 CIV12 CIV4 VID4 TS0 MS1 YLM4 CLM4 AR4 GPIOIN1 GOENB1 GPIOIN0 GOENB0 DVDD2 DSM P-OUTP DSEN SHF2 SHF1 SHF0 FSCI31 FSCI27 FSCI23 FSCI19 FSCI15 FSCI11 FSCI7 FSCI3 PLLS CIV24 CIV19 CIV11 CIV3 VID3 RSA MSO YLM3 CLM3 AR3 SCO2 FSCI30 FSCI26 FSCI22 FSCl18 FSCl14 FSCl10 FSCI6 FSCI2 PLL5VD ClVH1 CIV18 CIV10 CIV2 VID2 BST MTD YLM2 CLM2 AR2 SCO1 FSCI29 FSCI25 FSCI21 FSCl17 FSCl13 FSCl9 FSCI5 FSCI1 PLL5VA ClVH0 CIV17 CIV9 CIV1 VID1 NST YLM8 YLM1 CLM1 AR1 SCO0 FSCI28 FSCI24 FSCI20 FSCl16 FSCI12 FSCI8 FSCI4 FSCI0 MEM5V AClV CIV16 CIV8 CIVO VID0 TE CLM8 YLM0 CLM0 AR0 M7 N7 M6 N6 M5 N5 Reserved M4 N4 Reserved M3 N3 N9 M2 N2 N8 M1 N1 M8 M0 N0 YT CT CE2 CVBST CE1 SENSE CE0 SCART DES Reset* SYO PD2 VSP PD1 HSP PD0 BL7 HP7 VP7 BL6 HP6 VP6 BL5 HP5 VP5 BL4 HP4 VP4 BL3 HP3 VP3 CFRB SAV7 M/S* SAV6 Reserved SAV5 MCP SAV4 XCM1 SAV3 XCM0 SAV2 SAV8 BL2 HP2 VP2 PCM1 SAV1 HP8 BL1 HP1 VP1 PCM0 SAV0 VP8 BL0 HP0 VP0 FLFF CVBW DACG CBW1 Reserved CBW0 YPEAK IDF3 YSV1 IDF2 YSV0 IDF1 YCV IDF0
Bit 7
IR2
Bit 6
IR1
Bit 5
IRO FC1
Bit 4
VOS1 FC0
Bit 3
VOS0 FY1
Bit 2
SR2 FY0
Bit 1
SR1 FT1
Bit 0
SR0 FT0
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Register Descriptions (continued) Display Mode Register
CH7007A
Symbol: DMR Address: 00H Bits: 8
6
IR1 R/W 1
Bit: Symbol: Type: Default:
7
IR2 R/W 0
5
IR0 R/W 1
4
VOS1 R/W 0
3
VOS0 R/W 1
2
SR2 R/W 0
1
SR1 R/W 1
0
SR0 R/W 0
This register provides programmable control of the CH7007 display mode, including input resolution (IR[2:0]), output TV standard (VOS[1:0]), and scaling ratio (SR[2:0]). The mode of operation is determined according to the table below (default is 640x480 input, NTSC output, 7/8's scaling). Table 13. Display Modes
Input Data Format (Active Video)
512x384 512x384 512x384 512x384 720X400 720x400 720x400 720x400 640x400 640x400 640x400 640x400 640x400 640x480 640x480 640x480 640x480 640x480 640x480 800x600 800x600 800x600 800x600 800x600 800x600 720x576 720x480
Mode
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25* 26*
IR[2:0]
000 000 000 000 001 001 001 001 010 010 010 010 010 011 011 011 011 011 011 100 100 100 100 100 100 101 101
VOS [1:0]
00 00 01 01 00 00 01 01 00 00 01 01 01 00 00 00 01 01 01 00 00 00 01 01 01 00 01
SR [2:0]
000 001 000 001 000 001 000 001 010 001 000 001 010 000 001 011 001 010 011 001 011 100 011 100 101 001 001
Total Pixels/Line x Total Lines/Frame
840x500 840x625 800x420 784x525 1125X500 1116x625 945x420 936x525 1000x500 1008x625 840x420 840x525 840x600 840x500 840x625 840x750 784x525 784x600 800x630 944x625 960x750 936x836 1040x630 1040x700 1064x750 864x625 858x525
Output Format
PAL PAL NTSC NTSC PAL PAL NTSC NTSC PAL PAL NTSC NTSC NTSC PAL PAL PAL NTSC NTSC NTSC PAL PAL PAL NTSC NTSC NTSC PAL NTSC
Scaling
5/4 1/1 5/4 1/1 5/4 1/1 5/4 1/1 5/4 1/1 5/4 1/1 7/8 5/4 1/1 5/6 1/1 7/8 5/6 1/1 5/6 3/4 5/6 3/4 7/10 1/1 1/1
Pixel Clock (MHz)
21.000000 26.250000 20.139860 24.671329 28.125000 34.875000 23.790210 29.454545 25.000000 31.5000000 21.146853 26.433566 30.209790 21.000000 26.250000 31.5000000 24.671329 28.195804 30.209790 29.500000 36.0000000 39.000000 39.272727 43.636364 47.832168 13.500000 13.500000
* Interlaced modes of operation. (For those modes, some functions will be bypassed. For details, please contact the application department.)
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Register Descriptions (continued)
VOS[1:0] Output Format
00 PAL 01 NTSC 10 PAL-M 11
CH7007A
NTSC-J
Flicker Filter Register
Symbol: FFR Address: 01H Bits: 6
6 5
FC1 R/W 1
Bit: Symbol: Type: Default:
7
4
FC0 R/W 1
3
FY1 R/W 0
2
FY0 R/W 0
1
FT1 R/W 1
0
FT0 R/W 0
The flicker filter register provides for adjusting the operation of the various filters used in rendering the on-screen image. Adjusting settings between minimal and maximal values enables optimization between sharpness and flicker content. The FC[1:0] bits determine the settings for the chroma channel. The FT[1:0] bits determine the settings for the text enhancement circuit. The FY[1:0] bits determine the settings for the luma channel. In addition, the Chroma channel filtering includes a setting to enable the chroma dot crawl reduction circuit.
Note: When writing to register O1H, FY[1:0] is bits 3:2. FT[1:0] is bits 1:0. When reading from the register O1H, FY [1:0] is bits 1:0 and FT[1:0] is bits 3:2.
Table 14. Flicker Filter Settings
FY[1:0] 00 01 10 11 FT[1:0] 00 01 10 11 FC[1:0] 00 01 10 11 Settings for Luma Channel Minimal Flicker Filtering Slight Flicker Filtering Maximum Flicker Filtering Invalid Settings for Text Enhancement Circuit Maximum Text Enhancement Slight Text Enhancement Minimum Text Enhancement Invalid Settings for Chroma Channel Minimal Flicker Filtering Slight Flicker Filtering Maximum Flicker Filtering Enable Chroma DotCrawl Reduction
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Register Descriptions (continued) Video Bandwidth Register
CH7007A
Symbol: VBW Address: 03H Bits: 8
4
CBW0 R/W 0
Bit: Symbol: Type: Default:
7
FLFF R/W 0
6
CVBW R/W 0
5
CBW1 R/W 0
3
YPEAK R/W 0
2
YSV1 R/W 0
1
YSV0 R/W 0
0
YCV R/W 0
This register enables the selection of alternative filters for use in the luma and chroma channels. There are currently four filter options defined for the chroma channel, four filter options in the S-Video luma channel and two filter options in the composite luma channel. The Tables 15 and 16 below show the various settings. Table 15. Luma Filter Bandwidth
YCV
0 1 YSV[1:0] 00 01 10 11 YPEAK 0 1
Luma Composite Video Filter Adjust
Low bandwidth High bandwidth Luma S-Video Filter Adjust Low bandwidth Medium bandwidth High bandwidth Reserved Disables the Y-peaking circuit Disables the peaking filter in luma s-video channel Enables the peaking filter in luma s-video channel
Table 16. Chroma Filter Bandwidth
CBW[1:0]
00 01 10 11
Chroma Filter Adjust
Low bandwidth Medium bandwidth Med-high bandwidth High bandwidth
Bit 6 (CVBW) outputs the S-Video luma signal on both the S-Video luma output and the CVBS output. A 1 in this location enables the output of a black and white image on composite video, thereby eliminating the degrading effects of the color signal (such as dot crawl or false colors), which is useful for viewing text with high accuracy. Bit 7 (FLFF) controls the flicker filter used in the 7/10's scaling modes. In these scaling modes, setting FLFF to 1 causes a five line flicker filter to be used. The default setting of 0 uses a four line flicker filter.
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Register Descriptions (continued) Input Data Format Register
CH7007A
Symbol: IDF Address: 04H Bits: 6
5
Reserved R/W 0
Bit: Symbol: Type: Default:
7
6
DACG R/W 0
4
3
IDF3 R/W 0
2
IDF2 R/W 0
1
IDF1 R/W 0
0
IDF0 R/W 0
This register sets the variables required to define the incoming pixel data stream.
Table 17. Input Data Format
IDF[3:0]
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001-1111 Not available Not available Not available Not available 12-bit multiplexed RGB (24-bit color) input ("C" multiplex scheme) 12-bit multiplexed RGB (24-bit color) input ("I" multiplex scheme) Not available 8-bit multiplexed RGB (16-bit color, 565) input 8-bit multiplexed RGB (15-bit color, 555) input 8-bit multiplexed YCrCb (24-bit color) input (Y, Cr and Cb are multiplexed)
Description
Reserved (bit 5): This bit should be set to 0. DACG (bit 6): This bit controls the gain of the D/A converters. When DACG=0, the nominal DAC current is 71 A, which provides the correct levels for NTSC and PAL-M. When DACG=1, the nominal DAC current is 76A, which provides the correct levels for PAL and NTSC-J.
Clock Mode Register
Symbol: CM Address: 06H Bits: 8
6
M/S* R/W 0
Bit: Symbol: Type: Default:
7
CFRB R/W 0
5
Reserved R/W 0
4
MCP R/W 1
3
XCM1 R/W 0
2
XCM0 R/W 0
1
PCM1 R/W 0
0
PCM0 R/W 0
The setting of the clock mode bits determines the clocking mechanism used in the CH7007. The clock modes are shown in the table below. PCM controls the frequency of the P-OUT clock, and XCM identifies the frequency of the XCLK input clock.
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Register Descriptions (continued)
CH7007A
Note: Although it is possible to set the XCM [1:0] and PCM[1:0] values independent of the input data format, there are only certain combinations of input data format, XCM and PCM, that will result in valid data being demultiplexed at the input of the device. Refer to the "Input Data Format Register" for these combinations.
Note: Display modes 25 and 26 must use a 2X multiplexed input data format and a 2X XCLK. Table 18. Clock Mode Register
XCM[1:0]
00 00 00 01 01 01
PCM[1:0]
00 01 1X 00 01 1X
XCLK
1X 1X 1X 2X 2X 2X
P-Out
1X 2X 3X 1X 2X 3X
Input Data Modes Supported
4, 5, 7, 8, 9 4, 5, 7, 8, 9 4, 5, 7, 8, 9 4, 5, 7, 8, 9 4, 5, 7, 8, 9 4, 5, 7, 8, 9
The Clock Mode Register also contains the following bits: * MCP (bit 4) determines which edge of the pixel clock output will be used to latch input data. Zero selects the negative edge, one selects the positive edge. * M/S* (bit 6) determines whether the device operates in master or slave clock mode. In master mode (1), the 14.31818MHz clock is used as a frequency reference to the PLL. In slave mode (0) the XCLK input is used as a reference to the PLL, and is divided by the value specified by XCM[1:0]. The divide by N and M are forced to one. * CFRB (bit 7) sets whether the chroma subcarrier free-runs, or is locked to the video signal. One causes the subcarrier to lock to the TV vertical rate, and should be used when the ACIV bit is set to zero. Zero causes the subcarrier to free-run, and should be used when the ACIV bit is set to one.
Start Active Video Register
Symbol: SAV Address: 07H Bits: 8
5
SAV5 R/W 0
Bit: Symbol: Type: Default:
7
SAV7 R/W 0
6
SAV6 R/W 0
4
SAV4 R/W 0
3
SAV3 R/W 0
2
SAV2 R/W 0
1
SAV1 R/W 0
0
SAV0 R/W 0
This register sets the delay in pixel increments from leading edge of horizontal sync, or the rising edge of data start, to the start of active video. The entire bit field SAV[8:0] is comprised of this register SAV[7:0], plus the MSB value contained in the position overflow register, bit SAV8. This is decoded as a whole number of pixels, which can be set anywhere between 0 and 511 pixels. Therefore, in any 2X clock mode, the number of 2X clocks from the leading edge of sync to the first active data must be a multiple of two clocks. In any 3X clock mode, the number of 3X clocks from the leading edge of sync to the first active data must be a multiple of three clocks. When using the DS/BCO pin as a data start input, this register should be set to decimal value 11.
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Register Descriptions (continued) Position Overflow Register
CH7007A
Symbol: PO Address: 08H Bits: 3
5 4 3 2
SAV8 R/W 0
Bit: Symbol: Type: Default:
7
6
1
HP8 R/W 0
0
VP8 R/W 0
This position overflow register contains the MSB values for the SAV, HP and VP values, as follows: * * * VP8 (bit 0) is the MSB of the vertical position value (see explanation under "Vertical Position Register"). HP8 (bit 1) is the MSB of the horizontal position value (see explanation under "Horizontal Position Register"). SAV8 (bit 2) is the MSB of the start of active video value (see explanation under "Start Active Video Register").
Black Level Register
Symbol: BLR Address: 09H Bits: 8
6
BL6 R/W 1
Bit: Symbol: Type: Default:
7
BL7 R/W 0
5
BL5 R/W 1
4
BL4 R/W 1
3
BL3 R/W 1
2
BL2 R/W 1
1
BL1 R/W 1
0
BL0 R/W 1
This register sets the black level. The luminance data is added to this black level, which must be set between 90 and 208, with the default value being 127. Recommended values for NTSC and PAL-M are 127, 105 for PAL and 100 for NTSC-J.
Horizontal Position Register
Symbol: HPR Address: 0AH Bits: 8
5
HP5 R/W 0
Bit: Symbol: Type: Default:
7
HP7 R/W 0
6
HP6 R/W 0
4
HP4 R/W 0
3
HP3 R/W 0
2
HP2 R/W 0
1
HP1 R/W 0
0
HP0 R/W 0
The horizontal position register is used to shift the displayed TV image in a horizontal direction (left or right) to achieve a horizontally centered image on screen. The entire bit field, HP[8:0] is comprised of this register HP[7:0] plus the MSB value contained in the position overflow register, bit HP8. Increasing this value moves the displayed image position RIGHT; decreasing this value moves the displayed image position LEFT. Each increment moves the image position by 4 input pixels.
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Register Descriptions (continued) Vertical Position Register
CH7007A
Symbol: VPR Address: 0BH Bits: 8
5
VP5 R/W 0
Bit: Symbol: Type: Default:
7
VP7 R/W 0
6
VP6 R/W 0
4
VP4 R/W 0
3
VP3 R/W 0
2
VP2 R/W 0
1
VP1 R/W 0
0
VP0 R/W 0
This register is used to shift the displayed TV image in a vertical direction (up or down) to achieve a vertically centered image on screen. This bit field, VP[8:0] represents the TV line number (relative to the VGA vertical sync) used to initiate the generation and insertion of the TV vertical interval (i.e., the first sequence of equalizing pulses). Increasing values delay the output of the TV vertical sync, causing the image position to move UP on the TV screen. Decreasing values, therefore, move the image position DOWN. Each increment moves the image position by one TV lines (approximately 4 input lines). The maximum value that should be programmed into the VP[8:0] value is the number of TV lines minus one, divided by two (262, 312 or 313). When panning the image up, the number should be increased until (TVLPF-1) /2 is reached; the next step should be to reset the register to zero. When panning the image down the screen, the VP[8:0] value should be decremented until the value zero is reached. The next step should set the register to (TVLPF-1) /2, and then decrementing can continue. If this value is programmed to a number greater than (TV lines per frame-1) /2, a TV vertical SYNC will not be generated.
Sync Polarity Register
Symbol: SPR Address: 0DH Bits: 4
6 5 4 3
DES R/W 0
Bit: Symbol: Type: Default:
7
2
SYO R/W 0
1
VSP R/W 0
0
HSP R/W 0
This register provides selection of the synchronization signal input to, or output from, the CH7007. * HSP (bit 0) is Horizontal Sync Polarity - an HSP value of zero means the horizontal sync is active low and a value of one means the horizontal sync is active high. * VSP (bit 1) is Vertical Sync Polarity - a VSP value of zero means the vertical sync is active low and a value of one means the vertical sync is active high. * SYO (bit 2) is Sync Direction - a SYO value of zero means that H and V sync are input to the CH7007. A value of one means that H and V sync are output from the CH7007. * DES (bit 3) is Detect Embedded Sync - a DES value of zero means that H and V sync will be obtained from the direct pin inputs. A DES value of one means that H and V sync will be detected from the embedded codes on the pixel input stream. Note that this will only be valid for the YCrCb input modes.
Note: When sync direction is set to be an output, horizontal sync will use a fixed pulse width of 64 pixels and vertical sync will use a fixed pulse width of 1 line.
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Register Descriptions (continued) Power Management Register
CH7007A
Symbol: PMR Address: 0EH Bits: 5
5 4
SCART R/W 0
Bit: Symbol: Type: Default:
7
6
3
Reset* R/W 1
2
PD2 R/W 1
1
PD1 R/W 0
0
PD0 R/W 1
This register provides control of the power management functions, a software reset (Reset*) and the SCART output enable. The CH7007 provides programmable control of its operating states, as described in the table below. Table 19. Power Management
PD[2:0]
000 001 010 011 1XX
Operating State
Composite Off Power Down S-Video Off Normal (On) Full Power Down
Functional Description
CVBS DAC is powered down. Most pins and circuitry are disabled (except for the buffered clock outputs which are limited to the 14MHz output and VCO divided outputs). S-Video DACs are powered down. All circuits and pins are active. All circuitry is powered down except I2C circuit.
Reset* (bit 3) is soft reset. Setting this bit will reset all circuitry requiring a power on reset, except for this bit itself and the I 2 C state machines. SCART (bit 4) is the SCART enable. Setting SCART = 0 means the CH7007 will operate normally, outputting Y/C and CVBS from the three DACs. SCART=1 enables SCART output, which will cause R, G and B to be output from the DACs and composite sync from the CSYNC pin.
Note: For complete details regarding the operation of these modes, see the Power Management in Functional Description sections.
Connection Detect Register
Symbol: CDR Address: 10H Bits: 4
5 4 3
YT R 0
Bit: Symbol: Type: Default:
7
6
2
CT R 0
1
CVBST R 0
0
SENSE W 0
The Connection Detect Register provides a means to sense the connection of a TV to either S-Video or Composite video outputs. The status bits, YT, CT, and CVBST correspond to the DAC outputs for S-Video (Y and C outputs) and Composite video (CVBS), respectively. However, the values contained in these status bits are NOT VALID until a sensing procedure is performed. Use of this register requires a sequence of events to enable the sensing of outputs, then reading out the applicable status bits. The detection sequence works as follows: 1. Ensure the power management register bits 2-0 are set to 011 (normal mode).
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Register Descriptions (continued)
CH7007A
2. Ensure that the XCLK and XCLK* input pins are receiving clock signals (alternatively, XCLK* can be connected to the VREF pin). 3. Set the SENSE bit to a 1. This forces a constant current output onto the Y, C, and CVBS outputs. Note that during SENSE = 1, these 3 analog outputs are at steady state and no TV synchronization pulses are asserted. 4. Reset the SENSE bit to 0. This triggers a comparison between the voltage sensed on these analog outputs and the reference value expected (V threshold = 1.235V). If the measured voltage is below this threshold value, it is considered connected, if it is above this voltage it is considered unconnected. During this step, each of the three status bits corresponding to individual analog outputs will be set if they are NOT connected. 5. Read the status bits. The status bits Y, C and CVBST (corresponding to S-Video Y and C outputs and composite video) now contain valid information which can be read to determine which outputs are connected to a TV. Again, a "0" indicates a valid connection, a "1" indicates an unconnected output.
Contrast Enhancement Register
Symbol: CE Address: 11H Bits: 3
5 4 3 2
CE2 R/W 0
Bit: Symbol: Type: Default:
7
6
1
CE1 R/W 1
0
CE0 R/W 1
This register provides control of the contrast enhancement feature of the CH7007, according to the table below. At a setting of 000, the video signal will be pulled towards the maximum black level. As the value of CE[2:0] is increased, the amount that the signal is pulled towards black is decreased until unity gain is reached at a setting of 011. From this point on, the video signal is pulled towards the white direction, with the effect increasing with increasing settings of CE[2:0]. Table 20. Contrast Enhancement Function
CE[2:0]
000 001 010 011 100 101 110 111
Description (all gains limited to 0-255)
Contrast enhancement gain 3 Yout = (5/4)*(Yin-102) = Enhances Black Contrast enhancement gain 2 Yout = (9/8)*(Yin-57) Contrast enhancement gain 1 Yout = (17/16)*(Yin-30) Normal mode Yout = (1/1)*(Yin-0) = Normal Contrast Contrast enhancement gain 1 Yout = (17/16)*(Yin-0) Contrast enhancement gain 2 Yout = (9/8)*(Yin-0) Contrast enhancement gain 3 Yout = (5/4)*(Yin-0) Contrast enhancement gain 4 Yout = (3/2)*(Yin-0) = Enhances White
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Register Descriptions (continued)
CH7007A
256 224 192 160 128 96 64 32 0
0
32
64
96
128
160
192
224
256
Figure 24: Luma Transfer Function at different contrast enhancement settings.
PLL Overflow Register
Symbol: MNE Address: 13H Bits: 5
5 4
Reserved R/W 0
Bit: Symbol: Type: Default:
7
6
3
Reserved R/W 0
2
N9 R/W 0
1
N8 R/W 0
0
M8 R/W 0
The PLL Overflow Register contains the MSB bits for the'M' and 'N' values, which will be described in the PLL-M and PLL-N registers, respectively. The reserved bits should not be written to.
PLL M Value Register
Symbol: PLLM Address: 14H Bits: 8
6
M6 R/W 1
Bit: Symbol: Type: Default:
7
M7 R/W 0
5
M5 R/W 0
4
M4 R/W 0
3
M3 R/W 0
2
M2 R/W 0
1
M1 R/W 0
0
M0 R/W 1
The PLL M value register determines the division factor applied to the frequency reference clock before it is input to the PLL phase detector when the CH7007 is operating in master mode. In slave mode, an external pixel clock is used instead of the frequency reference, and the division factor is determined by the XCM[1:0] value. This register contains the lower 8 bits of the complete 9-bit M value.
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Register Descriptions (continued) PLL N Value Register
CH7007A
Symbol: PLLN Address: 15H Bits: 8
6
N6 R/W 0
Bit: Symbol: Type: Default:
7
N7 R/W 1
5
N5 R/W 0
4
N4 R/W 0
3
N3 R/W 0
2
N2 R/W 0
1
N1 R/W 0
0
N0 R/W 0
The PLL N value register determines the division factor applied to the VCO output before being applied to the PLL phase detector, when the CH7007 is operating in master mode. In slave mode, the value of `N' is always 1. This register contains the lower 8 bits of the complete 10-bit N value. The pixel clock generated in a master mode and is calculated according to the equation below: Fpixel = Fref* [(N+2) / (M+2)] When using a 14.318 MHz frequency reference, the required M and N values for each mode are shown in the table below Table 21. M and N Values for Each Mode
Mode
0 1 2 3 4 5 6 7 8 9 10 11 12 13
VGA Resolution, TV Standard, Scaling Ratio
512x384, PAL, 5:4 512x384, PAL, 1:1 512X384, NTSC, 5:4 512X384, NTSC, 1:1 720X400, PAL, 5:4 720X400, PAL, 1:1 720X400, NTSC, 5:4 720X400, NTSC, 1:1 640X400, PAL, 5:4 640X400, PAL, 1:1 640X400, NTSC, 5:4 640x400, NTSC, 1:1 640X400, NTSC, 7:8 640X480, PAL, 5:4
N 10bits
20 9 126 110 53 339 106 70 108 9 94 22 190 20
M 9bits
13 4 89 63 26 138 63 33 61 3 63 11 89 13
Mode
14 15 16 17 18 19 20 21 22 23 24 25 26
VGA Resolution, TV Standard, Scaling Ratio
640x480, PAL, 1:1 640X480, PAL, 5:6 640X480, NTSC, 1:1 640X480, NTSC, 7:8 640X480, NTSC, 5:6 800X600, PAL, 1:1 800X600, PAL, 5:6 800X600, PAL, 3:4 800X600, NTSC, 5:6 800X600, NTSC, 3:4 800X600, NTSC, 7:10 720X576, PAL, 1:1 720X480, NTSC, 1:1
N 10bits
9 9 110 126 190 647 86 284 94 62 302 31 31
M 9bits
4 3 63 63 89 313 33 103 33 19 89 33 33
Buffered Clock Output Register
Symbol: BCO Address: 17H Bits: 6
5
SHF2 R/W 0
Bit: Symbol: Type: Default:
7
6
4
SHF1 R/W 0
3
SHF0 R/W 0
2
SCO2 R/W 0
1
SCO1 R/W 0
0
SCO0 R/W 0
When this pin is selected to be an output, the buffered clock output register determines which clock is selected to be output at the DS/BCO clock output pin and what frequency value is output when a VCO derived signal is output. The tables below show the possible outputs.
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Register Descriptions (continued)
Table 22. Clock Output Selection
SCO[2:0]
000 001 010 011 100 101 110 111
CH7007A
Buffered Clock Output
14MHz crystal (for test use only) VCO divided by K3 (see Table23 ) Field ID signal (for test use only) (for test use only) TV horizontal sync (for test use only) TV vertical sync (for test use only)
Table 23. K3 Selection
SHF[2:0] 000 010 011 100 101 110 111 K3 2.5 3.5 4 4.5 5 6 7
Subcarrier Value Registers
Symbol: FSCI Address: 18H - 1FH Bits: 4 or 8 each
5 4 3
FSCI# R/W
Bit: Symbol: Type: Default:
7
6
2
FSCI# R/W
1
FSCI# R/W
0
FSCI# R/W
The lower four bits of registers 18H through 1FH contain a 32-bit value which is used as an increment value for the ROM address generation circuitry. The bit locations are specified as the following: Register 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH Contents FSCI[31:28] FSCI[27:24] FSCI[23:20] FSCI[19:16] FSCI[15:12] FSCI[11:8] FSCI[7:4] FSCI[3:0]
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Register Descriptions (continued)
CH7007A
When the CH7007 is operating in the master clock mode, the tables below should be used to set the FSCI registers. When using these values, the ACIV bit in register 21H should be set to "0" and the CFRB bit in register 06H should be set to "1". Table 24. FSCI Values (525-Line Modes)
Mode 2 3 6 7 10 11 12 16 17 18 22 23 24 26 NTSC "Normal Dot Crawl" 763,363,328 623,153,737 574,429,782 463,962,517 646,233,505 516,986,804 452,363,454 623,153,737 545,259,520 508,908,885 521,957,831 469,762,048 428,554,851 569,408,543 NTSC "No Dot Crawl" 763,366,524 623,156,346 574,432,187 463,964,459 646,236,211 5165,988,968 452,365,347 623,156,346 545,261,803 508,911,016 521,960,016 469,764,015 438,556,645 569,410,927 PAL-M "Normal Dot Crawl" 762,524,467 622,468,953 573,798,541 463,452,668 645,523,358 516,418,687 451,866,351 622,468,953 544,660,334 508,349,645 521,384,251 469,245,826 428,083,911 568,782,819
Table 25. FSCI Values (625-Line Modes)
Mode 0 1 4 5 8 9 13 14 15 19 20 21 25 PAL "Normal Dot Crawl" 806,021,060 644,816,848 601,829,058 485,346,014 677,057,690 537,347,373 806,021,060 644,816,848 537,347,373 645,499,916 528,951,320 488,262,757* 705,268,427 PAL-N "Normal Dot Crawl" 651,209,077 520,967,262 486,236,111 392,125,896 547,015,625 434,139,385 651,209,077 520,967,262 434,139,385 521,519,134 427,355,957 394,482,422 569,807,942
When the CH7007 is operating in the slave clock mode, the ACIV bit in register 21H should be set to "1" and the CFRB bit in register 06H should be set to "0". *Note: For reduced cross-color and cross-luminance artifacts, a value of 488,265,597 can be used with CFRB = "0" & ACIV = "0".
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Register Descriptions (continued)
CH7007A
Symbol: Address: 1BH Bits: 8
Bit: Symbol: Type: Default:
7
GPIOIN1 R/W 0
6
GPIOIN0 R/W 0
5
DVDD2 R/W 0
4
P-OUTP R/W 0
3
FSCI19 R/W 0
2
FSCI18 R/W 0
1
FSCI17 R/W 0
0
FSCI16 R/W 0
Register 1BH, bit 4 (P-OUTP) controls the polarity of the P-OUT pin. Register 1BH, bit 5 controls the P-OUT drive level, and should be set to 0 when DVDD2 is 1.8V, and set to 1 when DVDD2 is 3.3V. Register 1BH, bits 7 and 6 control the GPIO pins. When the corresponding GOENB bits are low, these registers values are driven out of the GPIO pins. When the corresponding GOENB bits are high, these registers values can be read to determine the level forced into the GPIO pins.
Symbol: Address: 1CH Bits: 6
Bit: Symbol: Type: Default: 7
GOENB1 R/W 1
6
GOENB0 R/W 1
5
DSM R/W 1
4
DSEN R/W 1
3
FSCI15 R/W 0
2
FSCI14 R/W 0
1
FSCI13 R/W 0
0
FSCI12 R/W 0
Register 1CH, bit 4 controls whether the Data Start pin or the Horizontal Sync pin is used to determine the start of active video. When this bit is low, the pin continues to operate as the BCO pin described in the BCO register section. When this bit is high the pin becomes an input for the Data Start signal. A value of 0 is recommended if H syn is used as a reference to active video and the DSM bit5 also need to be set to 0. Register 1CH, bit 5 determines how the Data Start input is used. A value of 0 is recommended, if DSEN bit4 is set to 0. Register 1CH, bits 7and 6 control the GPIO pins direction. When a GOENB bit is low, the corresponding GPIO pin is an output pin. When a GOENB bit is high, the corresponding GPIO pin can be read to determine the level forced into it.
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Register Descriptions (continued) PLL Control Register
CH7007A
Symbol: PLLC Address: 20H Bits: 6
6 5
PLLCPI R/W 0
Bit: Symbol: Type: Default:
7
4
PLLCAP R/W 0
3
PLLS R/W 1
2
PLL5VD R/W 0
1
PLL5VA R/W 1
0
MEM5V R/W 0
The following PLL and memory controls are available through the PLL control register: MEM5V PLL5VA PLL5VD PLLS PLLCAP PLLCPI MEM5V should be set to 0 when DVDD is 3.3 volts, and 1 when DVDD is 5 volts. PLL5VA is set to 1 when AVDD is 5 volts. PLL5VD is set to 1 when DVDD is 5 volts. A value of 0 is used when DVDD is 3.3 volts (default). When the PLL5VA is 1 PLLS should be 1. When PLL5VA is 0 PLLS should be 0. PLLCAP controls the loop filter capacitor of the PLL. A recommended listing of PLLCAP vs Mode is shown below. The default value should be used.
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Register Descriptions (continued)
Table 26. PLL Capacitor Setting
Mode
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
CH7007A
PLLCAP Value
1 1 1 0 1 0 1 1 0 1 1 1 0 1 1 1 0 0 0 0 1 0 1 1 0 1 1
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CIV Control Register
CH7007A
Symbol: CIVC Address: 21H Bits: 5
6 5 4
CIV25 R 0
Bit: Symbol: Type: Default:
7
3
CIV24 R 0
2
CIVH1 R/W 0
1
CIVH0 R/W 0
0
ACIV R/W 1
The following controls are available through the CIV control register: ACIV When the automatic calculated increment value is 1, the number calculated and present at the CIV registers will automatically be used as the increment value for subcarrier generation, removing the need for the user to read the CIV value and write in a new FSCI value. Whenever this bit is set to 1, the subcarrier generation must be forced to free-run mode (CFRB = 0). These bits control the hysteresis circuit which is used to calculate the CIV value. See descriptions in the next section.
CIVH[1:0] CIV[25:24]
Calculated Increment Value Register
Symbol: CIV Address: 22H - 24H Bits: 8
4
CIV# R 0
Bit: Symbol: Type: Default:
7
CIV# R 0
6
CIV# R 0
5
CIV# R 0
3
CIV# R 0
2
CIV# R 0
1
CIV# R 0
0
CIV# R 0
The CIV registers 22H through 24H contain a 26-bit value, which is the calculated increment value that should be used as the upper 26 bits of FSCI. This value is determined by a comparison of the pixel clock and the 14MHz clock. The bit locations and calculation of CIV are specified as the following: Register Contents 21H CIV[25:24] 22H CIV[23:16] 23H CIV[15:8] 24H CIV[7:0]
Version ID Register
Symbol: VID Address: 25H Bits: 8
6
VID6 R 1
Bit: Symbol: Type: Default:
7
VID7 R 0
5
VID5 R 0
4
VID4 R 1
3
VID3 R 0
2
VID2 R 0
1
VID1 R 0
0
VID0 R 0
This read-only register contains a 8-bit value indicating the identification number assigned to this version of the CH7007. The default value shown is pre-programmed into this chip and is useful for checking for the correct version of this chip, before proceeding with its programming.
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CH7007A
Address Register
Symbol: AR Address: 3FH Bits: 6
6
Reserved
Bit: Symbol: Type: Default:
7
Reserved
5
AR5 R/W X
4
AR4 R/W X
3
AR3 R/W X
2
AR2 R/W X
1
AR1 R/W X
0
AR0 R/W X
The Address Register points to the register currently being accessed.
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Electrical Specifications
Table 27. Absolute Maximum Ratings
Symbol Description
V DD relative to GND Input voltage of all digital pins1
CH7007A
Min - 0.5 GND - 0.5
Typ
Max 7.0 VDD + 0.5
Units V V Sec C C C C
TSC TAMB TSTOR TJ TVPS
Analog output short circuit duration Ambient operating temperature Storage temperature Junction temperature Vapor phase soldering (one minute)
Indefinite - 55 - 65 85 150 150 220
Notes:
1. Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions above those indicated under the normal operating condition of this specification is not recommended. Exposure to absolute maximum rating conditions for extended periods my affect reliability. 2. The device is fabricated using high-performance CMOS technology. It should be handled as an ESD sensitive device. Voltage on any signal pin that exceeds the power supply voltages by more than 0.5V can induce destructive latch. Table 28. Recommended Operating Conditions
Symbol VDD AVDD DVDD DVDD2 DVDD2 RL Description
DAC power supply voltage Analog supply voltage Digital supply voltage Digital supply voltage (P-OUT pin) VGA controller interface = 1.8V Digital supply voltage (P-OUT pin) VGA controller interface = 3.3V Output load to DAC outputs
Min
4.75 4.75 3.1 1.7 3.1
Typ
5.00 5.00 3.3 1.8 3.3 37.5
Max
5.25 5.25 3.6 1.9 3.6
Units
V
V V
Table 29. Electrical Characteristics (Operating Conditions: TA = 0 oC - 70 oC, VDD = 5V 5%)
Video D/A resolution Full scale output current Video level error VDD & AVDD (5V) current (simultaneous S-Video & composite outputs) DVDD (3.3V) current DVDD2 (1.8V) current (15pF load)
9
9 33.89
9 10
Bits mA % mA mA mA
105 45 4
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CH7007A
Timing Information
P-OUT
VOH VOL t36 t38 t39 t39
XCLK
VOH VOL
XCLK*
VOH VOL t37
D[11:0]
VOH P0a VOL t37 t40 P0b P1a P1b P2a P2b
DS
VOH VOL t37 t40
H
VOH 64 P-OUT VOL
V
VOH VOL t40
1 VGA Line t40
CK
(Internal Clock)
DVDD DGND DVDD DGND DVDD DGND
CKB
(Internal Clock)
PCLKX
(Internal Clock)
Symbol VOH VOL t36 t37 t38 t39 t40
DVDD2
Parameter
Output High level of interface signals Output Low level of interface signals (P-OUT = VREF) to (XCLK = XCLK*) Delay Setup and Hold time: Differential Clock: (XCLK = XCLK*) to (D[11:0], H, V & DS = VREF) Single-ended Clock: (XCLK =VREF) to (D[11:0], H, V & DS = VREF) XCLK & XCLK* rise/fall time w/15pF load P-OUT rise/fall time w/15pF load, VREF = 1.65 V D[11:0], H, V & DW rise/fall time w/15pF load Digital I/O Supply Voltage
Min
DVDD2 - 0.2 -0.2 2 1.5
Typ
Max
DVDD2 + 0.2 0.2 9
Unit
V V nS nS
1
3 3 2
7
nS nS nS
1.7
3.6
V
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Table 30. Digital Inputs / Outputs
Symbol
V SDOL V IICIH V IICIL V DATAIH V DATAIL V P-OUTOH V P-OUTOL
CH7007A
Description
SD Output Low Voltage SD Input High Voltage SD Input Low Voltage D[0-11] Input High Voltage D[0-11] Input Low Voltage P-OUT Output High Voltage P-OUT Output Low Voltage
Test Condition
IOL = 2.0 mA
Min
Typ
Max
0.4
Unit
V V V V V V
2.7 GND-0.5 Vref+0.25 GND-0.5 IOL = - 400 A IOL = 3.2 mA 2.8
VDD + 0.5 1.4 DVDD+0.5 Vref-0.25
0.2
V
Note:
V IIC -refers to I C pins SD and SC. V DATA - refers to all digital pixel and clock inputs. 2 V SD - refers to I C pin SD as an output. V P-OUT - refers to pixel data output Time - Graphics.
2
ORDERING INFORMATION
Part number CH7007A-V CH7007A-T Package type PLCC TQFP Number of pins 44 44 Voltage supply 3V/5V 3V/5V
Chrontel
2210 O'Toole Avenue San Jose, CA 95131-1326 Tel: (408) 383-9328 Fax: (408) 383-9338 www.chrontel.com E-mail: sales@chrontel.com
(c)1998 Chrontel, Inc. All Rights Reserved. Chrontel PRODUCTS ARE NOT AUTHORIZED FOR AND SHOULD NOT BE USED WITHIN LIFE SUPPORT SYSTEMS OR NUCLEAR FACILITY APPLICATIONS WITHOUT THE SPECIFIC WRITTEN CONSENT OF Chrontel. Life support systems are those intended to support or sustain life and whose failure to perform when used as directed can reasonably expect to result in personal injury or death. Chrontel reserves the right to make changes at any time without notice to improve and supply the best possible product and is not responsible and does not assume any liability for misapplication or use outside the limits specified in this document. We provide no warranty for the use of our products and assume no liability for errors contained in this document. Printed in the U.S.A.
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